1. Field of the Invention
The present invention relates to a method of programming a flash memory cell and, more particularly, to a method of programming a flash memory cell capable of being applied to an NAND flash memory device.
2. Discussion of Related Art
Recently, semiconductor memory devices which are electrically programmable, erasable, and capable of storing data, even when power is not supplied, have been increasingly demanded. Also, a high integration technology of a memory cell has been developed to develop a high capacity memory device capable of storing a large amount of data. For this purpose, an NAND flash memory device, in which a plurality of memory cells are serially connected to form a string and a plurality of the strings constitute a memory cell array, has been proposed.
Each flash memory cell of the NAND flash memory device include a current passage between a source and a drain on a semiconductor substrate, and a floating gate and a control gate connected with insulators interposed between there on the semiconductor substrate. In addition, a typical programming operation of the flash memory cell is accomplished by grounding bulk areas, semiconductor substrates, and source areas of the memory cells, applying a high positive voltage, which is called a programming voltage Vpp of, e.g., 15V to 20V, and applying the voltage of, e.g., 5V to 6V, to the drain for programming the memory cells so as to generate hot carriers. The hot carriers are generated in such a way that electrons in the bulk area are accumulated in a floating gate by the electric field of the high voltage Vpp applied to the control gate and electrons supplied to the drain area are continuously accumulated.
FIG. 1 is a circuit diagram showing a typical NAND flash memory.
1st to 16th cells (c1 to c16) are serially connected in a first string st1. A drain of the first cell c1 is connected to a first bit line b1 through a string selection transistor d. A source of the 16th cell c16 is connected to a common source line s1 through a source selection transistor s. The second string st2 has the same structure as the first string st1. Gates of the cells in the same horizontal line are connected to the respective word lines. Though it is not apparently shown in the drawing, a flash memory is composed of a plurality of strings, as described above.
The voltage of 0V is applied to the bit line selected during the programming, whereas a power supply voltage Vcc is applied to the unselected bit line. In addition, a voltage Vpgm of, e.g., 18V is applied to the selected word line, the voltage of e.g., 4.5V is applied to a drain selection line DSL1, and the voltage of 0V is applied to a source selection line SSL1. Also, the voltage of, e.g., 10V is applied to the unselected word lines. Then, the cells selected by such a voltage condition are individually programmed.
Now, the conventional programming method will be further described in detail with reference to FIG. 2.
At the beginning of the programming, the aforementioned programming voltages are applied to the selected cells during one pulse period so as to execute a programming operation (Step 100). Then, it is verified whether the programming operation is normally accomplished or not(Step 110). As a result, if the programming is normally accomplished, the programming is terminated. Otherwise, the programming is returned to the above Step 100 to execute the programming operation again.
According to such a programming method, the cells can be over-programmed. The over-programmed cells determine a gate bias Vpp applied to the unselected cells during a read-out operation. If this bias is increased by the over-programmed voltage, a program disturbance occurs in the read-out operation by such a bias. A method of improving these shortcomings is shown in FIG. 3.
FIG. 3 is a flow chart for explaining another conventional programming method.
At the beginning of the programming, the aforementioned programming voltages are applied to the selected cells during one pulse period (that is, a cycle) so as to execute a programming operation (Step 200). Then, it is verified whether the programming operation is normally accomplished or not (Step 210). As a result, if the programming is normally accomplished, the programming is terminated. Otherwise, the programming is returned to the above Step 200 after incrementing the gate programming voltage (Step 220) to execute the programming operation again. Such a programming method is called an incremental step pulse programming (ISPP). According to such a programming method, some of the cells can be over-programmed by the width of the pulse.
FIG. 4 shows a threshold voltage distribution according to the number of the cells after the programming. Herein, a solid line indicates a threshold voltage distribution when the programming is normally accomplished, whereas the dotted line indicates a threshold voltage distribution when the over-programming occurs.